1. Field of the Invention
The present invention relates to a memory cell and a memory array utilizing the memory cell, and particularly relates to the structure of a memory cell and a memory array.
2. Description of the Prior Art
A conventional DRAM cell includes a bit line, a word line, a switch device (always be a transistor) and a capacitor. The capacitor is utilized to store data when it is charged or discharged (logic value 0 or 1). The switch device is turned on or off via a word line. The bit line is utilized to transmit the data read from the capacitor of the memory cell, or the data written to the capacitor, when the switch device to the memory cell is turned on.
With the advancement of semiconductor processing technologies, the size of semiconductor devices is shrinking. Accordingly, the sizes of DRAM cells are also becoming smaller, thus significantly reducing the distances between bit lines. As a result, adjacent bit lines may suffer undesirable coupling effect and generate noise to each other. As a result, data transmitted by bit lines in such a device may therefore be wrongly determined. For example, data 0 may be wrongly determined to be 1, and data 1 may be wrongly determined to be 0.